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1 mx25u5121e, mx25u1001e datasheet mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
2 contents 1. features .............................................................................................................................................................. 4 general .................................................................................................................................................. 4 performance ....................................................................................................................................... 4 software features ........................................................................................................................... 4 hardware features .......................................................................................................................... 5 2. general description ..................................................................................................................................... 5 3. pin configurations ......................................................................................................................................... 6 8-land uson (2x3mm) ........................................................................................................................... 6 4. pin description .................................................................................................................................................. 6 5. block diagram ................................................................................................................................................... 7 6. memory organization ..................................................................................................................................... 8 table 1. memory organization (512kb) ..................................................................................................... 8 table 2. memory organization (1mb) ........................................................................................................ 8 7. device operation .............................................................................................................................................. 9 figure 1. serial modes supported ................................................................................................................ 9 8. hold feature .................................................................................................................................................... 10 figure 2. hold condition operation ........................................................................................................... 10 9. data protection .............................................................................................................................................. 11 table 3. protected area sizes ................................................................................................................. 11 10. command description ................................................................................................................................. 12 table 4. command set ............................................................................................................................ 12 10-1. w rite enable (wren) .............................................................................................................................. 13 10-2. w rite disable (wrdi) .............................................................................................................................. 13 10-3. read identifcation (rdid) ....................................................................................................................... 13 table 5. id defnitions ............................................................................................................................. 13 10-4. read status register (rdsr) ................................................................................................................. 14 table 6. status register ........................................................................................................................... 14 10-5. w rite status register (wrsr) ................................................................................................................ 15 table 7. protection modes ...................................................................................................................... 15 10-6. read data bytes (read) ........................................................................................................................ 16 10-7. read data bytes at higher speed (f ast_read) .................................................................................. 16 10-8. dual read mode (dread) ...................................................................................................................... 16 10-9. 4 x i/o read mode (4read) ................................................................................................................... 16 10-10. sector erase (se) .................................................................................................................................... 17 10-11. block erase (be) ..................................................................................................................................... 17 10-12. chip erase (ce) ....................................................................................................................................... 17 10-13. page program (pp) ................................................................................................................................. 18 10-14. deep power-down (dp) .......................................................................................................................... 18 10-15. release from deep power-down (rdp) ................................................................................................. 18 11. power-on state ............................................................................................................................................. 19 mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
3 figure 3. program/erase fow with read array data .................................................................................... 20 12. electrical specifications ........................................................................................................................ 21 12-1. absolute maximum ra tings .......................................................................................................... 21 figure 4. maximum negative overshoot waveform ................................................................................... 21 12-2. cap acitance ta = 25c, f = 1.0 mhz .................................................................................................. 21 figure 5. maximum positive overshoot waveform .................................................................................... 21 figure 6. input test waveforms and measurement level .......................................................................... 22 figure 7. output loading ............................................................................................................................ 22 table 8. dc characteristics ........................................................................................................... 23 table 9. ac characteristics .......................................................................................................... 24 13. timing analysis .................................................................................................................................................. 25 figure 8. serial input timing ....................................................................................................................... 25 figure 9. output timing .............................................................................................................................. 25 figure 10. wp# disable setup and hold timing during wrsr when srwd=1 ........................................ 26 figure 11. write enable (wren) sequence (command 06) ...................................................................... 26 figure 12. write disable (wrdi) sequence (command 04) ...................................................................... 26 figure 13. read identifcation (rdid) sequence (command 9f) .............................................................. 27 figure 14. read status register (rdsr) sequence (command 05) ........................................................ 28 figure 15. write status register (wrsr) sequence (command 01) ....................................................... 28 figure 16. read data bytes (read) sequence (command 03) ............................................................... 28 figure 17. read at higher speed (fast_read) sequence (command 0b) ........................................... 29 figure 18. dual read mode sequence (command 3b) ............................................................................. 29 figure 19. 4 x i/o read mode sequence (command eb) ......................................................................... 30 figure 20. sector erase (se) sequence (command 20) .......................................................................... 30 figure 21. block erase (be) sequence (command d8 or 52) .................................................................. 31 figure 22. chip erase (ce) sequence (command 60 or c7) ................................................................... 31 figure 23. page program (pp) sequence (command 02) ........................................................................ 31 figure 24. deep power down (dp) sequence (command b9) ................................................................. 32 figure 25. release from deep power down (rdp) sequence (command ab) ........................................ 32 figure 26. power-up timing ....................................................................................................................... 33 table 10. power-up timing ...................................................................................................................... 33 13-1. initial delivery state ...................................................................................................................... 33 14. operating conditions ................................................................................................................................. 34 figure 27. ac timing at device power-up ................................................................................................. 34 figure 28. power-down sequence ............................................................................................................. 35 15. erase and programming performance .............................................................................................. 36 17. data retention ............................................................................................................................................. 36 16. latch-up characteristics ........................................................................................................................ 36 18. ordering information ................................................................................................................................ 37 19. part name description ............................................................................................................................... 38 20. package information .................................................................................................................................. 39 mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
4 512k-bit [x 1/x 4] cmos mxsmio ? serial flash memory 1m-bit [x 1/x 4] cmos mxsmio ? serial flash memory 1. features general 6huldo 3hulskhudo ,qwhuidfh frpsdwleoh 0rgh dqg 0rgh ? 512kb: 524,288 x 1 bit structure or 131,072 x 4 bit structure 1mb: 1,048,576 x 1 bit structure or 262,144 x 4 bit structure (txdo 6hfwruv zlwk . ewhv hdfk .e 32 equal sectors with 4k bytes each (1mb) - any sector can be erased individually (txdo %orfnv zlwk . ewhv hdfk 512kb ) 2 equal blocks with 64k bytes each (1mb) - any block can be erased individually 3urjudp &dsdelolw - byte base - page base (32 bytes) 6lqjoh 3rzhu 6xsso 2shudwlrq - 1.65 to 2.0 volt for read, erase, and program operations /dwfkxs surwhfwhg wr p iurp 9 wr 9ff 9 performance 3huirupdqfh - normal read: - 30mhz - fast read: - 1 i/o: 70mhz with 8 dummy cycles - 2 i/o: 70mhz with 8 dummy cycles, equivalent to 140mhz - 4 i/o: 60mhz with 6 dummy cycles, equivalent to 240mhz - fast program time: 360us(typ.) and 1.3ms(max.)/page - fast erase time: 120ms (typ.)/sector ; 1.3sec (typ.)/block /rz 3rzhu &rqvxpswlrq - low active read current: 5ma(max.) at 30mhz, 10ma(max.) at 70mhz - low active programming current: 25ma (max.) - low active erase current: 25ma (max.) - low standby current: 25ua (typ.) - deep power down current: 3ua (typ.) 7 slfdo hudvhsurjudp ffohv hduv gdwd uhwhqwlrq software features ,qsxw dwd )rupdw - 1-byte command code %orfn /rfn surwhfwlrq 7kh %3a%3 vwdwxv elwv ghqhv wkh vlh ri wkh duhd wr eh vriwzduh surwhfwhg djdlqvw 3urjudp dqg (udvh instructions xwr (udvh dqg xwr 3urjudp ojrulwkp xwrpdwlfdoo hudvhv dqg yhulhv gdwd dw vhohfwhg vhfwru xwrpdwlfdoo surjudpv dqg yhulhv gdwd dw vhohfwhg sdjh e dq lqwhuqdo dojrulwkp wkdw dxwrpdwlfdoo wlphv wkh mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
5 2. general description the device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. the device provides sequential read operation on the whole chip. after program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci - fed page or sector locations will be executed. program command is executed on page (32 bytes) basis, and erase command is executes on sector, or block, or whole chip. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. when the device is not in operation and cs# is high, it is put in standby mode and draws less than 35ua (typical:25ua) dc current. the device utilizes macronix proprietary memory cell, which reliably stores memory contents even after typical 100,000 program and erase cycles. program pulse widths (any page to be programed should have page in the erased state frst) ? status register feature electronic identifcation - jedec 1-byte manufacturer id and 2-bytes device id hardware features sclk input - serial clock input ? si/sio0 - serial data input or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? so/sio1 - serial data output or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? wp#/sio2 - hardware write protection or serial data input/output for 4 x i/o read mode ? hold#/sio3 - pause the chip without diselecting the chip or serial data input/output for 4 x i/o read mode ? package - 8-pin sop (150mil) - 8-pin tssop (173mil) - 8-uson (2x3mm) - all devices are rohs compliant and halogen-free mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
6 3. pin configurations 4. pin description 8-pin tssop (173mil) symbol description cs# chip select si/sio0 serial data input or serial data input/output for 2 x i/o read mode and 4 x i/o read mode so/sio1 serial data output or serial data input/output for 2 x i/o read mode and 4 x i/o read mode sclk clock input hold#/sio3 pause the chip without diselecting the chip or serial data input/output for 4 x i/o read mode wp#/sio2 hardware write protection or serial data input/output for 4 x i/o read mode vcc +1.8v power supply gnd ground 1 2 3 4 cs# so/sio1 wp#/sio2 gnd vcc hold#/sio3 sclk si/sio0 8 7 6 5 8-pin sop (150mil) 1 2 3 4 cs# so/sio1 wp#/sio2 gnd vcc hold#/sio3 sclk si/sio0 8 7 6 5 8-land uson (2x3mm) 1 2 3 4 cs# so/sio1 wp#/sio2 gnd 8 7 6 5 vcc hold#/sio3 sclk si/sio0 mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
7 5. block diagram address generator memory array page buffer y-decoder x-decoder data register sram buffer si/sio0 sclk so/sio1 clock generator state machine mode logic sense amplifier hv generator output buffer cs# wp#/sio2 hold#/sio3 mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
8 table 1. memory organization (512kb) table 2. memory organization (1mb) 6. memory organization block sector address range 0 15 00f000h 00ffffh : : : 3 003000h 003fffh 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh block sector address range 1 31 01f000h 01ffffh : : : 16 010000h 010fffh 0 15 00f000h 00ffffh : : : 3 003000h 003fffh 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
9 7. device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended op - eration. 2. when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps the standby mode until next cs# falling edge. in standby mode, all so pins of this lsi should be high-z. 3. when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next cs# rising edge. 4. input data is latched on the rising edge of serial clock(sclk) and data shifts out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown as "figure 1. serial modes supported" . 5. for the following instructions: rdid, rdsr, read, f ast_read and 4read the shifted-in instruction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the follow - ing instructions: wren, wrdi, wrsr, se, be, ce, pp, rdp, and dp the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. during the progress of program, erase operation, to access the memory array is neglected and not affect the current operation of program and erase. figure 1. serial modes supported note: cpol indicates clock polarity of serial master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported. sclk msb cpha shift in shift out si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
10 8. hold feature hold# pin signal goes low to hold any serial communications with the device. the hold feature will not stop the operation of write status register, programming, or erasing in progress. the operation of hold requires chip select (cs#) keeping low and starts on falling edge of hold# pin signal while serial clock (sclk) signal is being low (if serial clock signal is not being low, hold operation will not start until se - rial clock signal being low). the hold condition ends on the rising edge of hold# pin signal while serial clock (sclk) signal is being low (if serial clock signal is not being low, hold operation will not end until serial clock being low), see"figure 2. hold condition operation" . figure 2. hold condition operation the serial data output (so) is high impedance, both serial data input (si) and serial clock (sclk) are don't care during the hold operation. if chip select (cs#) drives high during hold operation, it will reset the internal logic of the device. to re-start communication with chip, the hold# must be at high and cs# must be at low. hold# cs# sclk hold condition (standard) hold condition (non-standard) mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
11 9. data protection during power transition, there may be some false system level signals which result in inadvertent erasure or programming. the device is designed to protect itself from these accidental write cycles. the state machine will be reset as standby mode automatically during power up. in addition, the control register architecture of the device constrains that the memory contents can only be changed after specifc command sequences have completed successfully. in the following, there are several features to protect the system from the accidental write cycles during vcc powerup and power-down or from system noise. ? valid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? write enable (wren) command: wren command is required to set the w rite enable latch bit (wel) before other command to change data. the wel bit will return to reset stage under following situation: - power-up - w rite disable (wrdi) command completion - w rite status register (wrsr) command completion - page program (pp) command completion - sector erase (se) command completion - block erase (be) command completion - chip erase (ce) comma nd completion ? software protection mode (spm): by using bp0-bp1 bits to set the part of flash protected from data change. ? hardware protection mode (hpm): by using wp# going low to protect the bp0-bp1 bits and sr wd bit from data change. ? deep power down mode: by entering deep power down mode, the fash device also is under protected from writing all commands except release from deep power down mode command (rdp). table 3. protected area sizes status bit protect level bp1 bp0 mx25u5121e mx25u1001e 0 0 0 (none) 0 (none) 0 1 1 (all) 1 (1 block) 1 0 2 (all) 2 (all) 1 1 3 (all) 3 (all) mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
12 10. command description table 4. command set command (byte) wren (write enable) wrdi (write disable) wrsr (write status register) rdid (read ident ifc- ation) rdsr (read status register) read (read data) fast read (fast read data) 1st byte 06 (hex) 04 (hex) 01 (hex) 9f (hex) 05 (hex) 03 (hex) 0b (hex) 2nd byte ad1 ad1 3rd byte ad2 ad2 4th byte ad3 ad3 5th byte dummy data cycles action sets the (wel) write enable latch bit resets the (wel) write enable latch bit to write new values of the status register outputs jedec id: 1-byte manufacturer id & 2-bytes device id to read out the values of the status register n bytes read out until cs# goes high n bytes read out until cs# goes high command (byte) dread (1i/2o read) 4read (4 i/o read) se (sector erase) be (block erase) ce (chip erase) pp (page program) dp (deep power down) 1st byte 3b (hex) eb (hex) 20 (hex) 52 or d8 (hex) 60 or c7 (hex) 02 (hex) b9 (hex) 2nd byte ad1 ad1 ad1 ad1 ad1 3rd byte ad2 ad2 ad2 ad2 ad2 4th byte ad3 ad3 ad3 ad3 ad3 5th byte dummy dummy data cycles 1-32 action n bytes read out by 2 x i/ o until cs# goes high n bytes read out by 4 x i/ o until cs# goes high to erase the selected sector to erase the selected block to erase whole chip to program the selected page enters deep power down mode command (byte) rdp (release from deep power down) 1st byte ab (hex) 2nd byte 3rd byte 4th byte 5th byte data cycles action release from deep power down mode note 1: it is not recommend ed to adopt any other code not in the command defnition table, which will potentially enter the hidden mode. note 2: value "0" should be input to the un-used signifcant bits of address bits by user (e.g. a17~a23(msb) in mx25u1001e ; a16-a23(msb) in mx25u5121e) mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
13 10-1. write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, se, be, ce and wrsr which are intended to change the device content, should be set every time after the wren in - struction setting the wel bit. the sequence of issuing w ren ins truction is: cs # goes low sending w ren ins truction code cs# goes high. (pleas e refer to "figure 11. write enable (wren) sequence (command 06)" ) 10-2. write disable (wrdi) the write disable (wrdi) instruction is for resetting write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes lowsending wrdi instruction codecs# goes high. (please refer to "figure 12. write disable (wrdi) sequence (command 04)" ) the wel bit is reset by following situations: - power-up - w rite disable (wrdi) instruction completion - w rite status register (wrsr) instruction completion - page program (pp) instruction completion - sector erase (se) instruction completion - block erase (be) instruction completion - chip erase (ce) instruction completion 10-3. 5hdg,ghqwlfdwlrq5, the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-bytes. the macronix manufacturer id is c2(hex), the memory type id is 25(hex) as the frst-byte device id, and the indi - vidual device id of second-byte id are listed as "table 5. id defnitions" . the sequence of issuing rdid instruction is: cs# goes lowsending rdid instruction code24-bits id data out on so to end rdid operation can use cs# to high at any time during data out. (please refer to "figure 13. read identifcation (rdid) sequence (command 9f)" ) while program/erase operation is in progress, it will not decode the rdid instruction, so there's no effect on the cy - cle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby mode. table 5. ,hqlwlrqv rdid command mx25u5121e mx25u1001e manufacturer id memory type memory density manufacturer id memory type memory density c2 25 30 c2 25 31 mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
14 10-4. read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase condition) and continuously. it is recommended to check the write in progress (wip) bit before sending a new instruction when a program or erase operation is in progress. the sequence of issuing rdsr instruction is: cs# goes lowsending rdsr instruction codestatus register data out on so (please refer to "figure 14. read status register (rdsr) sequence (command 05)" ) the defnition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase progress. when wip bit sets to 1, which means the device is busy in program/erase progress. when wip bit sets to 0, which means the device is not in progress of program/erase register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase instruction. when wel bit sets to 0, which means no internal write enable latch; the device will not accept program/erase instruction. bp1, bp0 bits. the block protect (bp1, bp0) bits, volatile bits, indicate the protected area(as defned in "table 3. protected area sizes" ) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp1, bp0) bits requires the write status register (wrsr) instruction to be executed. those bits defne the protected area of the memory to against page program (pp), sector erase (se), block erase (be) and chip erase(ce) instructions (only if all block protect bits set to 0, the ce instruction can be executed) qe bit. the quad enable (qe) bit, volatile bit, while it is "0" (factory default), it performs non-quad and wp# is en - able. while qe is "1", it performs quad i/o mode and wp# is disabled. in the other word, if the system goes into four i/o mode (qe=1), the features of hpm and hold will be disabled. srwd bit. the status register write disable (srwd) bit, volatile bit, is operated together with write protection ( wp#/ sio2 ) pin for providing hardware protection mode. the hardware protection mode requires srwd sets to 1 and wp#/sio2 pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp1, bp0) are read only. table 6. status register note: 1. see the "table 3. protected area sizes" . the default bp0-bp1 values are "1" (protected). 2. the srwd default value is "0" bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write protect) qe (quad enable) reserved reserved bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable 1=quad enable 0=not quad enable 0 0 (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
15 10-5. write status register (wrsr) the wrsr instruction is for changing the values of status register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in ad - vance. the wrsr instruction can change the value of block protect (bp1, bp0) bits to defne the protected area of memory (as shown in "table 3. protected area sizes" ). the wrsr also can set or reset the status register write disable (srwd) bit in accordance with write protection (wp#) pin signal. the wrsr instruction cannot be execut - ed once the hardware protected mode (hpm) is entered. the sequence of issuing wrsr instruction is: cs# goes low o sending wrsr instruction code o status register data on si o cs# goes high. (see "figure 15. write status register (wrsr) sequence (command 01)" ) the wrsr instruction has no effect on b5, b4, b1, b0 of the status register. the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. table 7. protection modes note: 1. as defned by the values in the block protect (bp1, bp0) bits of the status register , as shown in "table 3. protected area sizes". as the table above showing, the summary of the software protected mode (spm) and hardware protected mode (hpm). software protected mode (spm): - when srwd bit=0, no matter wp# is low or high, the wren instruction may set the wel bit and can change the values of sr wd, bp1, bp0. the protected area, which is defned by bp1, bp0, is at software protected mode (spm). - when sr wd bit=1 and wp# is high, the wren instruction may set the wel bit can change the values of srwd, bp1, bp0. the protected area, which is defned by bp1, bp0, is at software protected mode (spm) note: if srwd bit=1 but wp# is low, it is impossible to write the status register even if the wel bit has previ - ously been set. it is rejected to write the status register and not be executed. hardware protected mode (hpm): - when sr wd bit=1, and then wp# is low (or wp# is low before srwd bit=1), it enters the hardware protected mode (hpm). the data of the protected area is protected by software protected mode by bp1, bp0 and hard - ware protected mode by the wp# to against data modifcation. note: - to exit the hardware protected mode requires wp# driving high once the hardware protected mode is entered. if the wp# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via bp1, bp0. - if the system had entered the quad i/o (qe=1) mode, the feature of hpm will be disabled. mode status register condition wp# and srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp0-bp1 bits can be changed wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be program or erase. hardware protection mode (hpm) the srwd, bp0-bp1 of status register bits cannot be changed wp#=0, srwd bit=1 the protected area cannot be program or erase. mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
16 10-6. read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fc. the frst address can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. this product does not provide the function of read around. after reading through density 512kb or 1mb, cs# must go high. otherwise, the data correctness will not be guaranteed. if the device needs to read data again, it must issue read command once more. the sequence of issuing read instruction is: cs# goes low sending read instruction code 3-bytes address on sidata out on soto end read operation can use cs# to high at any time during data out. (please refer to "figure 16. read data bytes (read) sequence (command 03)" ) 10-7. read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing f ast_read instruction is: cs# goes low sending f ast_read instruction code 3-byte address on si 8 dummy cycles on sidata out on so to end f ast_read operation can use cs# to high at any time during data out. ( please refer to "figure 17. read at higher speed (fast_read) sequence (command 0b)") while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any im - pact on the program/erase/write status register current cycle. 10-8. dual read mode (dread) the dread instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits (interleave on 2 i/o pins) shift out on the falling edge of sclk at a maxi - mum frequency ft . the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single dread instruc - tion. the address counter rolls over to 0 when the highest address has been reached. once writing dread instruc - tion, the following data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing dread instruction is: cs# goes low o sending dread instruction o 3-byte address on si o 8-bit dummy cycle o data out interleave on so1 & so0 o to end dread operation can use cs# to high at any time during data out. (please refer to "figure 18. dual read mode sequence (command 3b)" ) 10-9. 4 x i/o read mode (4read) the 4read instruction enable quad throughput of serial flash in read mode. a quad enable (qe) bit of status register must be set to "1" before sending the 4read instruction. the address is latched on rising edge of sclk, and data of every four bits (interleave on 4 x i/o pins) shift out on the falling edge of sclk at a maximum frequency fc. the frst address can be at any location. the address is automatically increased to the next higher address af - ter each byte data is shifted out, so the whole memory can be read out at a single 4read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 4read instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
17 the sequence of issuing 4read instruction is: cs# goes low sending 4read instruction 24-bit address inter - leave on sio3, sio2, sio1 & sio0 6 dummy cycles data out interleave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out. ( please refer to )ljxuh,25hdg0rgh sequence (command eb)" ) 10-10. sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-bytes sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit be - fore sending the sector erase (se). any address of the sector (please refer to "table 1. memory organization (512kb)" and "table 2. memory organization (1mb)" ) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the eighth bit of last address byte been latched-in); otherwise, the instruction will be rejected and not executed. address bits [am-a12] (am is the most signifcant address) select the sector address. the sequence of issuing se instruction is: cs# goes lowsending se instruction code3-bytes address on si cs# goes high. (please refer to "figure 20. sector erase (se) sequence (command 20)" ) the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in pro - gress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tse timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. 10-11. block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k-byte sector erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the block erase (be). any address of the block (see "table 1. memory organization (512kb)" and "table 2. memory organization (1mb)" ) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence is shown as "figure 21. block erase (be) sequence (command d8 or 52)" . the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in pro - gress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tbe timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. 10-12. chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruc - tion must execute to set the write enable latch (wel) bit before sending the chip erase (ce). any address of the sector (see "table 1. memory organization (512kb)" and "table 2. memory organization (1mb)" ) is a valid address for chip erase (ce) instruction. the cs# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence is shown as "figure 22. chip erase (ce) sequence (command 60 or c7)" . the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in pro - gress (wip) bit still can be check out during the chip erase cycle is in progress. the wip sets 1 during the tce tim - ing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
18 10-13. page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the page program (pp). after the instruction and address input, data to be programmed is input sequentially. the internal sequence controller will sequentially program the data from the initial address. if the transmitted data goes beyond the page boundary, the internal se - quence controller may not function properly and the content of the device will not be guaranteed. therefore, if the initial a4-a0 (the fve least signifcant address bits) are set to all 0, maximum 32 bytes of data can be input sequen - tially. if the initial address a4-a0 (the fve least signifcant address bits) are not set to all 0, maximum bytes of data input will be the subtraction of the initial address a4-a0 from 32bytes. the data exceeding 32bytes data is not sent to device. in this case, data is not guaranteed. the sequenc e of issuing pp ins truction is: cs# goes low sending pp ins truction code 3-byt es addr ess on si at leas t 1- byte on dat a on s i cs # goes high. ( please r efer t o "figure 23. page program (pp) sequence (command 02)") the cs# must be kept to low during the whole page program cycle; the cs# must go high exactly at the byte boundary( the eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the page program cycle is in progress. the wip sets 1 during the tpp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. 10-14. deep power-down (dp) the deep power down (dp) instruction is for setting the device on the minimizing the power consumption (to enter - ing the deep power down mode), the standby current is reduced from isb1 to isb2. the deep power down mode requires the deep power down (dp) instruction to enter, during the deep power down mode, the device is not ac - tive and all read/write/program/erase instruction are ignored. the sequence of issuing dp instruction is: cs# goes lowsending dp instruction code cs# goes high. (please refer to )ljxuh'hhs3rzhu'rzq'36htxhqfh&rppdqg% ) once the dp instruction is set, all instruction will be ignored except the release from deep power down mode (rdp) instruction. when power-down, the deep power down mode automatically stops, and when power-up, the device automatically is in standby mode. for rdp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power down mode. 10-15. release from deep power-down (rdp) the release from deep power down (rdp) instruction is terminated by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the standby mode. if the device was not previously in the deep power down mode, the transition to the standby mode is immediate. if the device was previously in the deep pow - er down mode, though, the transition to the standby mode is delayed by tres1, and chip select (cs#) must re - main high for at least tres1(max), as specifed in "table 9. ac characteristics" . once in the standby mode, the device waits to be selected, so that it can receive, decode and execute instructions. the rdp instruction is only for releasing from deep power down mode. the sequence is shown as "figure 25. release from deep power down (rdp) sequence (command ab)" . even in deep power down mode, the rdp is also allowed to be executed, only except the device is in progress of pro - gram/erase cycle; there's no effect on the current program/erase cycle in progress. mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
19 11. power-on state the device is at below states when power-up: - standby mode ( please n ote it is not deep power down mode) - w rite enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the vcc achieves below correct level: - vcc minimum at power- up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. for further protection on the device, if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the read, write, erase, and program command should be sent after the below time delay: - tvsl after vcc reached vcc minimum level note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommend - ed. (generally around 0.1uf) mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
20 wr en co mm and program /erase co mm and write progr am data/address (w ri te erase address) rdsr command read array data (same add ress of pgm/ers) program /er ase su ccessfully yes yes program /erase fail no start verify ok? wip=0? progr am /e rase anot her bl ock? prog ram /er ase comp let ed no yes no rds r command* yes wel=1? no rdsr command read wel=0 figure 3. program/erase fow with read array data mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
21 12. electrical specifications 12-1. absolute maximum ratings notice: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot to vcc+1.0v or -1.0v for period up to 20ns. 12-2. capacitance ta = 25c, f = 1.0 mhz figure 4. maximum negative overshoot waveform figure 5. maximum positive overshoot waveform rating value ambient operating temperature industrial grade -40c to 85c storage temperature -65c to 150c applied input voltage -0.5v to vcc+0.5v applied output voltage -0.5v to vcc+0.5v vcc to ground potential -0.5v to 2.5v 0v -1.0v 20ns vcc+1.0v 2.0v 20ns symbol parameter min. typ. max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
22 figure 6. input test waveforms and measurement level figure 7. output loading ac measurement level input timing reference level output timing reference level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns device under test cl 25k ohm 25k ohm +1.8v cl=30pf including jig capacitance mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
23 table 8. dc characteristics notes : 1. typical values at vcc = 1.8v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. typical value is calculated by simulation. 3. not 100% tested. symbol parameter notes min. typ. max. units test conditions ili input load current 1 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max, vout = vcc or gnd isb1 vcc standby current 1 25 35 ua vin = vcc or gnd, cs# = vcc isb2 deep power down current 3 10 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 10 ma f=70mhz, sclk=0.1vcc/0.9vcc, so=open 5 ma f=30mhz, sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 20 25 ma program in progress, cs# = vcc icc3 vcc write register (wrsr) current 1 20 ma program status register in progress, cs#=vcc icc4 vcc sector erase current (se) 1 20 25 ma erase in progress, cs#=vcc vil input low voltage -0.5 0.2vcc v vih input high voltage 0.8vcc 9&& v vol output low voltage 0.2 v iol = 100ua voh output high voltage vcc-0.2 v ioh = -100ua vwi command inhibit voltage 3 1.0 1.4 v mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
24 table 9. ac characteristics notes: 1. tch + tcl must be greater than or equal to 1/ f (fc). 2. value guaranteed by characterization, not 100% tested in production. 3. test condition is shown as "figure 6. input test waveforms and measurement level" & "figure 7. output loading" . 4. only applicable as a constraint for a wrsr instruction when srwd is set at 1. symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for the following instructions: fast_read, pp, se, be, ce, dp, rdp, wren, wrdi, rdid, rdsr, wrsr 1khz 70 mhz frsclk fr clock frequency for read instruction 1khz 30 mhz ftsclk ft clock frequency for dread instruction 1khz 70 mhz fq clock frequency for 4read instruction 1khz 60 mhz tch(1) tclh clock high time serial (fsclk) 7 ns normal read (frsclk) 15 ns tcl(1) tcll clock low time serial (fsclk) 7 ns normal read (frsclk) 15 ns tclch(2) clock rise time (3) (peak to peak) 0.1 v/ns tchcl(2) clock fall time (3) (peak to peak) 0.1 v/ns tslch tcss cs# active setup time (relative to sclk) 7 ns tchsl cs# not active hold time (relative to sclk) 5 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 5 ns tchsh cs# active hold time (relative to sclk) 5 ns tshch cs# not active setup time (relative to sclk) 7 ns tshsl(4) tcsh cs# deselect time read 12 ns write/erase/program 30 ns tshqz(2) tdis output disable time 8 ns thlch hold# active setup time (relative to sclk) 4 ns tchhh hold# active hold time (relative to sclk) 4 ns thhch hold# not active setup time (relative to sclk) 4 ns tchhl hold# not active hold time (relative to sclk) 4 ns thhqx tlz hold# to output low-z 8 ns thlqz thz hold# to output high-z 8 ns tclqv tv clock low to output valid @ 30pf 8 ns @ 15pf 6 ns tclqx tho output hold time 1 ns twhsl(4) write protect setup time 20 ns tshwl(4) write protect hold time 100 ns tdp(2) cs# high to deep power down mode 10 us tres1(2) cs# high to standby mode without electronic signature read 10 us tw write status register cycle time 5 15 ms tpp page program cycle time (32 bytes) 0.36 1.3 ms tse sector erase cycle time (4k bytes) 120 400 ms tbe block erase cycle time 1.3 3 s tce chip erase cycle time 512kb 1.3 3 s 1mb 2.6 6 s mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
25 figure 8. serial input timing figure 9. output timing 13. timing analysis sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl lsb addr.lsb in tshqz tch tcl tclqx tclqv tclqx tclqv sclk so cs# si mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
26 figure 10. wp# disable setup and hold timing during wrsr when srwd=1 high-z 01 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so figure 11. write enable (wren) sequence (command 06) figure 12. write disable (wrdi) sequence (command 04) 21 34567 high-z 0 06 command sclk si cs# so 21 34567 high-z 0 04 command sclk si cs# so mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
27 figure 13. read identifcation (rdid) sequence (command 9f) 21 345678 9 10 11 12 13 14 15 command 0 manufacturer id high-z msb 15 14 13 3210 device id msb 7 6 5 3 2 1 0 16 17 18 28 29 30 31 sclk si cs# so 9f mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
28 figure 14. read status register (rdsr) sequence (command 05) 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05 sclk si cs# so 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 7654 3 1 7 0 data out 1 24-bit address 0 msb msb 2 39 data out 2 03 high-z command figure 15. write status register (wrsr) sequence (command 01) 21 345678 9 10 11 12 13 14 15 status register in 0 76543 2 0 1 msb sclk si cs# so 01 high-z command figure 16. read data bytes (read) sequence (command 03) mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
29 figure 17. read at higher speed (fast_read) sequence (command 0b) 23 21 3456789 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35 sclk si cs# so sclk si cs# so 0b command high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 30 31 32 39 40 41 43 44 45 42 3b d4 d5 d2 d3 d7 d6 d6 d4 d0 d7 d5 d1 command 24 add cycle 8 dummy cycle a23 a22 a1 a0 data out 1 data out 2 figure 18. dual read mode sequence (command 3b) mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
30 figure 19. 4 x i/o read mode sequence (command eb) figure 20. sector erase (se) sequence (command 20) 24 bit address 21 3456789 29 30 31 0 23 22 2 1 0 msb sclk cs# si 20 command note: 1. hi-impedance is inhibited for the two clock cycles. high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 1210 11 13 14 ebh address bit20, bit16..bit0 address bit21, bit17..bit1 data bit4, bit0, bit4.... data bit5 bit1, bit5.... 15 16 17 18 19 20 21 22 23 n high impedance wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... high impedance hold#/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 8 bit instruction 6 address cycles 6 dummy cycles data output mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
31 figure 21. block erase (be) sequence (command d8 or 52) note: be command is d8(hex) or 52(hex). 24 bit address 21 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si d8 or 52 command figure 22. chip erase (ce) sequence (command 60 or c7) note: ce command is 60(hex) or c7(hex). 21 34567 0 60 or c7 sclk si cs# command 4241 43 44 45 46 47 48 49 50 52 53 54 55 40 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 24-bit address 0 76543 2 0 1 data byte 1 39 51 76543 2 0 1 data byte 2 76543 2 0 1 data byte 3 data byte 32 287 286 285 284 283 282 281 76543 2 0 1 280 msb msb msb msb msb sclk cs# si sclk cs# si 02 command figure 23. page program (pp) sequence (command 02) mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
32 figure 24. deep power down (dp) sequence (command b9) 21 34567 0 t dp deep power down mode standby mode sclk cs# si b9 command figure 25. release from deep power down (rdp) sequence (command ab) 21 34567 0 t res1 standby mode deep power down mode high-z sclk cs# si so ab command mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
33 figure 26. power-up timing note: vcc (max.) is 2.0v and vcc (min.) is 1.65v. v cc v cc (min) chip selection is not allowed tvsl time device is fully accessible v cc (max) 13-1. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). note: 1. the parameter is characterized only. table 10. power-up timing symbol parameter min. max. unit tvsl(1) vcc(min) to cs# low 300 us mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
34 notes : 1. sampled, not 100% tested . 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the fgure, please refer to "table 9. ac characteristics". symbol parameter notes min. max. unit tvr vcc rise time 1 10 500000 us/v 14. operating conditions at device power-up and power-down ac timing illustrated in "figure 27. ac timing at device power-up" and "figure 28. power-down sequence" are for the supply voltages and the control signals at device power-up and power-down. if the timing in the fgures is ig - nored, the device will not operate correctly. during power-up and power-down, cs# needs to follow the voltage applied on vcc to keep the device not to be selected. the cs# can be driven low when vcc reach vcc(min.) and wait a period of tvsl. figure 27. ac timing at device power-up sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
35 figure 28. power-down sequence cs# sclk vcc during power-down, cs# needs to follow the voltage drop on vcc to avoid mis-operation. mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
36 15. erase and programming performance note: 1. t ypical program and erase time assumes the following conditions: 25 c, 1.8v, and checkerboard pattern. 2. under worst conditions of 85 c and 1.65v. 6vwhpohyho ryhukhdg lv wkh wlph uhtxluhg wr hhfxwh wkh uvwexvffoh vhtxhqfh iru wkh surjudpplqj frp - mand. 4. erase/program cycles comply with jedec jesd-47e & a117a standard. 16. latch-up characteristics parameter min. typ. (1) max. (2) unit sector erase time 120 400 ms block erase time 1.3 3 s chip erase time 512kb 1.3 3 s 1mb 2.6 6 s page program time (32 bytes) 0.36 1.3 ms erase/program cycle 100,000 cycles min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v 9&& 9 current -100ma p includes all pins except vcc. test conditions: vcc = 1.8v, one pin at a time. 17. data retention parameter condition min. max. unit data retention & 20 years mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
37 18. ordering information part no. clock (mhz) temperature package remark mx25u5121emi-14g 70 -40 c~85 c 8-sop (150mil) mx25u5121eoi-14g 70 -40 c~85 c 8-tssop (173mil) mx25u5121ezui-14g 70 -40 c~85 c 8-uson (2x3mm) 512kb part no. clock (mhz) temperature package remark mx25u1001emi-14g 70 -40 c~85 c 8-sop (150mil) mx25u1001eoi-14g 70 -40 c~85 c 8-tssop (173mil) mx25u1001ezui-14g 70 -40 c~85 c 8-uson (2x3mm) 1mb mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
38 19. part name description mx 25 u 14 m i g option: g: rohs compliant and halogen-free speed: 14: 70mhz temperature range: i: industrial (-40c to 85c) package: m: 150mil 8-sop o: 173mil 8-tssop zu: 2x3mm 8-uson density & mode: 5121e: 512kb 1001e: 1mb type: u: 1.8v device: 25: serial flash 1001e mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
39 20. package information mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
40 mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
41 mx25u5121e mx25u1001e p/n: pm1980 rev. 0.00, oct. 11, 2013 advanced information
42 macronix international co., ltd. reserves the right to change product and specifcations without notice. mx25u5121e mx25u1001e ([fhsw iru fxvwrpl]hg surgxfwv zklfk kdv ehhq h[suhvvo lghq wlhg lq wkh dssolfdeoh duhhphqw 0dfurql[v products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. in the event macronix products are used in contradicted to their wdujhw xvdjh deryh wkh exhu vkdoo wdnh dq dqg doo dfwlrqv wr hqvxuh vdlg 0dfurqlv surgxfw txdolhg iru lwv actual use in accordance with the applicable laws and regulations; and macronix as well as its suppliers and/or distributors shall be released from any and all liability arisen therefrom. copyright? macronix international co., ltd. 2013. all rights reserved, including the trademarks and tradename thereof, such as macronix, mxic, mxic logo, mx logo, integrated solutions provider, nbit, nbit, nbiit, macronix nbit, eliteflash, hybridnvm, hybridflash, xtrarom, phines, kh logo, be-sonos, ksmc, kingtech, mxsmio, macronix vee, macronix map, rich au dio, rich book, rich tv, and fitcam. the names dqg eudqgv ri wklug sduw uhihuuhg wkhuhwr li dq duh iru lghqwlfdwlrq sxusrvhv rqo for the contact and order information, please visit macronixs web site at: http://www.macronix.com

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